IEEE Transactions on Nuclear Science · 1995 · 43 citations · 2 references
EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDetector TechnologyLow-noise Circuit DesignLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignSemiconductor DetectorsComparator DesignComparatorsLow-noise Detector DesignLow-power Cmos DesignSilicon DetectorsSilicon Semiconductor DetectorsSilicon Strip DetectorsStrip Detectors
We have designed and tested a 64 channel amplifier-comparator integrated circuit on the Maxim SHPi bipolar process. The low power design, 840 /spl mu/W/channel, is intended for use as a frontend with high clock rate silicon strip detector systems. Peaking time at the comparator input is 20 ns, for good double pulse resolution, and noise is near optimum for the technology used. We have used the chip successfully in a proton beam test at KEK in Japan with a 40 MHz data clock.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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