60 GHz transmitter circuits in 65nm CMOS

Abstract

This work presents fundamental building blocks for a 60 GHz transmitter front-end. The circuits are implemented in a 65 nm bulk CMOS technology, operate from a 1.2 V supply, and attain state-of-the-art performance for multi-Gb/s wireless applications. A single-stage, single-ended, power amplifier achieves peak power gain of 4.5 dB, output 1 dB compression point of 6 dBm, saturated power of 9 dBm, and peak power added efficiency of 8.5% at 62 GHz. A double-balanced, Gilbert-based, up-conversion mixer achieves 6.5 dB of conversion loss and output 1 dB compression point of -5.0 dBm with LO of 50 GHz and IF of 10 GHz. Millimeter-wave design considerations and measurements over frequency and temperature are discussed.