A Novel CMOS Full Adder

Abstract

This paper proposes a high-speed adder cell using a new design style called "bridge". The bridge design style offers more regularity and higher density than conventional CMOS design style, by using some transistors, named bridge transistors. Results show 4.4% (@ Vdd=3 volt) to 34.1% (@ Vdd=1 volt) improvement in speed over conventional CMOS adder. HSPICE is the circuit simulator used, and the technology being used for simulations is BSIM3v3 0.18mum technology