Switched-capacitor decimators combining low-sensitivity ladder structures with high-speed polyphase networks

Abstract

High-order Switched-Capacitor (SC) decimation circuits that achieve high input sampling ratios while minimizing the required operating speed of the amplifiers have been previously designed by cascading simpler first- and second-order decimation building blocks. This paper proposes alternative SC decimators combining low-sensitivity ladder structures together with high-speed polyphase networks. This is based on the transformation of the state equation of a conventional SC ladder filter clocked at the higher sampling frequency MF/sub s/ into a multirate transfer function yielding a decimating structure with the same filtering characteristic and input sampling frequency of MF/sub s/ but where the output sampling frequency is reduced to only F/sub s/ to allow more time for the settling of the amplifiers. Two design examples of low-pass and band-pass SC decimators are given to illustrate the proposed design methodology. Detailed computer-based sensitivity analyses are carried-out to evaluate the performance of the resulting circuits.