2009 · 11 citations · 6 references
EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice CharacterizationDevice ReliabilityIntegrated Circuit DesignSemiconductor ReliabilityCmos ReliabilityInput ProtectionRobustness Testing Methodology
Abstract- Adiabatic failures due to an initial peak voltage of VF-TLP measurements were observed at the input gate of a 40nm CMOS technology. Moreover, a correlation was verified between the failure current of the VF-TLP measurements and failure voltage of CDM testing. Through the transient analyses by a VF-TLP system, the performance of a diode-stack was better than that of SCRs as an input protection for CDM robustness. I.
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Reliability aspects of gate oxide under ESD pulse stress
Adrien Ille, Wolfgang Stadler, T. Pompl et al. · 2007 · 45 citations
Engineering, Electrical Engineering, Electronic Materials +13