An 11b 70 MHz 1.2 mm 2 49mW 0.18 um CMOS ADC with on–chip current/voltage references

Abstract

This work proposes an 11b 70MHz CMOS pipelined A/D converter (ADC) as one of core circuit blocks for high-speed VDSL system applications. The proposed ADC for the internal use has the strictly limited number of externally connected I/O pins while the ADC employs on-chip CMOS current/voltage (I/V) references and a merged-capacitor switching (MCS) technique to improve ADC performances. The ADC implemented in a 0.18µm n-well single-poly quad-metal CMOS technology shows the maximum SNDR of 60 dB at 70 MSample/s. The ADC maintains the SNDR of 58 dB and the SFDR of 68 dB for input frequencies up to the Nyquist rate at 60 MSample/s. The measured DNL and INL of the ADC are within ±0.63 and ±1.21 LSB, respectively. The active chip area is 1.2 mm2and the ADC consumes 49 mW at 70 MSample/s at a 1.8 V supply.