Generalized low-error area-efficient fixed-width multipliers

Abstract

In this paper, we extend our previous methodology for designing a family of low-error area-efficient fixed-width two's-complement multipliers that receive two n-bit numbers and produce an n-bit product. The generalized methodology involving four steps results in several better error-compensation biases. These better error-compensation biases can be easily mapped to low-error area-efficient fixed-width multipliers suitable for very large-scale integration implementation and digital signal processing application. Via the proposed Type 1 8 /spl times/ 8 fixed-width multiplier, the reduction of the average error can be improved by 88% compared with the direct-truncated (D-Truncated) multiplier. It is also shown that the same proposed multiplier leads to 32.75% reduction in area compared with the standard multiplier.