FPGA implementation of an integer MIPS processor in Handel-C and its application to human face detection

Abstract

We present an FPGA implementation of an integer-based MIPS processor using the Handel-C hardware design language (HDL). The processor is implemented on the RC200 development board from Celoxica. The processor implementation is modified from the standard MIPS architecture to take into account the limitations and features of the board. A face detection system is implemented with the processor to show its application towards real-time image processing.