IEEE Transactions on Circuits and Systems I Regular Papers · 2009 · 14 citations · 20 references
EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsSystem-on-chip DesignAnalog FiltersAnalog Integrated CircuitsCmos Circuit DesignDigital Signal ProcessingMixed-signal Integrated Circuit DesignReceiver SystemsAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital ConvertersCmos Analog Circuit DesignCmos Analog Integrated CircuitsFrequency Shift KeyingLow-pass FiltersSensitivity
A fully integrated 2-MHz Gaussian frequency-shift keying (GFSK) analog front end for low-IF receivers is presented. The analog GFSK demodulation uses a Bessel-based quadrature discriminator and a differentiator-based data decision circuit, eliminating the need for analog-digital converters while enabling high sensitivity and large frequency offset tolerance. The analog front end consists of a fifth-order Butterworth low-pass prefilter, a seven-stage limiter, a quadrature discriminator with a fourth-order Bessel phase-shift network, a fourth-order Butterworth low-pass postfilter, and a differentiator-based data decision circuit. The prefilter, Bessel phase shifter, postfilter, and differentiator are built using identical <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Gm</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> cells and tuned across process variations with a single master-slave phase-locked loop. The GFSK analog front end is implemented in a 1.8-V 0.18-mum CMOS process, recovering 1-Mb/s input data from a 2-MHz GFSK signal with maximum frequency deviation of plusmn160-kHz, frequency offset tolerance from - 38% to +47%, and input sensitivity of -53 dBm and consuming 7 mA of current.
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