Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications

TLDR

Asynchronous implementations measure logic delays at runtime and activate registers accordingly, offering greater robustness than synchronous designs that rely on worst‑case delay estimates to constrain clock cycles. Desynchronization automates the conversion of synchronous specifications into asynchronous circuits, enabling broad adoption without requiring specialized design skills or tools. The authors analyze and formally prove the correctness of various desynchronization protocols, present a taxonomy of asynchronous latch controller protocols, and introduce a new controller that achieves provably maximal concurrency while evaluating its performance against the original synchronous implementation. The approach is demonstrated to be feasible and effective on real designs, including a complete implementation of the DLX microprocessor architecture.

Abstract

Asynchronous implementation techniques, which measure logic delays at runtime and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst case delays at design time and constrain the clock cycle accordingly. Desynchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus, permitting widespread adoption of asynchronicity without requiring special design skills or tools. In this paper, different protocols for desynchronization are first studied, and their correctness is formally proven using techniques originally developed for distributed deployment of synchronous language specifications. A taxonomy of existing protocols for asynchronous latch controllers, covering, in particular, the four-phase handshake protocols devised in the literature for micropipelines, is also provided. A new controller that exhibits provably maximal concurrency is then proposed, and the performance of desynchronized circuits is analyzed with respect to the original synchronous optimized implementation. Finally, this paper proves the feasibility and effectiveness of the proposed approach by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architecture