A CMOS beta multiplier voltage reference with improved temperature performance and silicon tunability

Abstract

A new implementation has been proposed for the beta multiplier voltage reference to improve its performance with regard to process variations. The scope for silicon tunability on the proposed circuit is also discussed. The circuit was implemented in a 0.18 /spl mu/ process and was found to have a temperature sensitivity of less than 500 ppm/C in the virgin die without trimming.