Transaction-level models for AMBA bus architecture using SystemC 2.0

Abstract

The concept of a SOC platform architecture introduces the concept of a communication infrastructure. In the transaction-level a finite set of architecture components (memories, arithmetic units, address generators, caches, etc) communicate among each other over shared resources (buses). Until recently, modeling architectures required pin-level hardware descriptions, typically coded in RTL. Great effort is required to design and verify the models, and simulation at this level of detail is tediously slow. Transaction level modeling is the solution. Transaction level models (TLMs) effectively create an executable platform model that simulates orders of magnitude faster than a RTL model. In this paper, we present a SystemC 2.0 TLM of the AMBA architecture developed by ARM, oriented to SOC platform architectures.