A unified decomposition approach for fault location in large analog circuits

Abstract

This paper deals with the problem of fault location in analog circuits. The circuit under test is decomposed into subnetworks using nodes at which voltages have been measured. We localize the faults to within the smallest possible subnetworks according to the final decomposition. Then, further identification of the faulty elements inside the subnetworks is carried out. The method is applicable to large-networks, linear or nonlinear. It requires a limited-number of measurement nodes and its on-line computation requirements are minimal. The method is based on checking the consistency of KCL in the decomposed circuit. A measure of the effect of tolerances on the elements is introduced, and a number of examples are considered to illustrate the application of the method in both the linear and the nonlinear cases.