Design methodology for a one-shot Reed-Solomon encoder and decoder

Abstract

The design methodology for a high-performance and compact one-shot Reed-Solomon encoder/decoder realized as a combinational circuit is presented. Under a two-level optimization approach, a combination of new encoding/decoding algorithms enabling highly parallel, yet shared architecture, and logic optimization methods tuned for huge-scale Galois field arithmetic operations, improves the circuit size and speed significantly. The higher level optimization not only can be entirely independent of the gate level optimization, but also further augments the advantages in the gate level optimization. As a result a (40-34,32)RS encoders/decoder soft IP-core achieving 45 ns latency and >7 Gb/s peak throughput without pipelining is realized using <90 K cells under 0.35 um CMOS gate-array technology.