2003 · 60 citations · 12 references
EngineeringComputer EngineeringComputer ScienceAutomationFormal MethodsReal-time SystemsAutomata TheoryFinite State Machine ModelingModel CheckingProgrammable Logic ControllersReal-time Systems DesignTiming ModelingAutomata In Formal VerificationPlc Hardware ArchitectureReal-time System VerificationReal-time Systems ModelingReal-time Systems VerificationTimed AutomataTimed Automata VerificationTimed Finite State Machines
We give timed automaton models for a class of Programmable Logic Controller (PLC) applications, that are programmed in a simple fragment of the language Instruction Lists as defined in the standard IEC 1131-3. Two different approaches for modelling timers are suggested, that lead to two different timed automaton models. The purpose of this work is to provide a basis for verification and testing of real-time properties of PLC applications. Our work can be seen in broader context: it is a contribution to methodical development of provably correct programs. Even if the present PLC hardware will be substituted by e.g. Personal Computers, with a similar operation mode, the development and verification method will remain useful.
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