A 622-MHz interpolating ring VCO with temperature compensation and jitter analysis

Abstract

A 622-MHz interpolating VCO has been designed using a 0.72 /spl mu/m CMOS technology for use as a clock recovery circuit in ATM Sonet OC-12 applications. A temperature compensated biasing scheme is adopted so that the VCO maintains its center frequency and tuning range throughout the temperature range 0/spl deg/C-130/spl deg/C. Simulation shows the sensitivity of the VCO center frequency achieves -100ppm//spl deg/C. Jitter analysis indicates an rms timing jitter due to thermal noise to be 365-fs. Power consumption is 65-mW from a 5-V supply.