SEU resistance in advanced SOI-SRAMs fabricated by commercial technology using a rad-hard circuit design

Abstract

We fabricate 128 Kbit SRAMs using a rad-hard circuit design based on a mixed-mode three-dimensional simulation in a commercial silicon-on-insulator foundry with 0.2 /spl mu/m design rules. Appropriate design increases the critical linear energy transfer of single-event upset over 164.4 MeV/(mg/cm/sup 2/).