Variable-Conversion-Ratio Switched-Capacitor-Voltage-Multiplier/Divider DC-DC Converter

Yuen‐Haw Chang

IEEE Transactions on Circuits and Systems I Regular Papers · 2011 · 42 citations · 20 references

Concepts

Abstract

An interleaved scheme of variable-conversion-ratio (VCR) multistage switched-capacitor-voltage-multiplier/divider (SCVM/SCVD) converter is proposed by combining a VCR-based phase generator and pulse-width-modulation (PWM) controller to integrate step-up and down modes in one structure for high-efficiency conversion. The power part consists of two m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> -stage SC cells (front) and two n <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> -stage SC cells (rear) in series for step-up/down gain of m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> × n <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> or 1/(m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> × n <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) at most. Here, VCR-based phase generator is suggested with changing the running stage number m, n and topological path to obtain a suitable gain of m × n or 1/(m × n) (m = 1, 2,..., m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> , n = 1,2,..., n <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) for improving efficiency, especially for the lower desired output. Besides, PWM is adopted to enhance output regulation as well as robustness to source/loading variation. Further, some theoretical analysis and design include: formulation, steady-state analysis, conversion ratio, efficiency, output ripple, stability, capacitance selection, and control design. Finally, the closed-loop SCVM/SCVD is simulated, and the hardware is implemented and tested. All results are illustrated to show the efficacy of this scheme.

References

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