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Effect of Furnace Preanneal and Rapid Thermal Annealing on Arsenic‐Implanted Silicon
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1985
Year
Materials ScienceSemiconductor TechnologyElectrical EngineeringIon ImplantationEngineeringCrystalline DefectsArsenic‐implanted SiliconApplied PhysicsRapid Thermal AnnealingImpurity DistributionSemiconductor Device FabricationFurnace PreannealSilicon On InsulatorDopant ActivationDopant DiffusionSemiconductor Device
In this paper, the effect of low temperature preanneal followed by rapid thermal annealing on arsenic‐implanted Si is studied. The electrical properties and impurity distribution of the annealed Si are discussed. Sheet mobility and dopant activation of the implanted Si (100) samples (As+: 80 keV, doses) as functions of annealing temperature are reported. TEM measurements on samples with and without preanneal (550°C, 1h) are presented. RBS and channeling results on samples with and without preanneal are also included. It is found that the dopant diffusion during RTA of dose As implants can be reduced somewhat by employing a 550°C, 1h furnace preanneal prior to RTA. However, the preanneal does not have significant effect on the carrier profiles of the dose implants. In some cases, the preanneal increases the dopant activation slightly.