Design and implementation of operational amplifiers with programmable characteristics in a 90nm CMOS process

Abstract

Operational amplifiers (op-amps) serve as the basic building blocks in almost every analog and mixed-signal electronic circuit. However, one of the most common problems in op-amp design is the variation in the op-amp's performance caused by process variations during fabrication. As such, it is of utmost importance that provisions be made on the op-amp to compensate for possible deviations in performance after chip fabrication. In this paper, a procedure on integrating programmable bias networks into an operational amplifier is developed. The programmable network driven by digital input words makes the output bias currents and voltages variable, thus making the op-amp tunable for proper operation even after chip fabrication. Furthermore, the programmability of other op-amp parameters such as gain, slew rate, and compensation are explored to increase the capability and flexibility of the op-amp. The programmability schemes are employed on two base op-amp topologies namely, the Two-stage Miller and the Folded Cascode. The project is implemented in a standard 90 nm CMOS process.