A novel parallel deadlock detection algorithm and architecture

Abstract

A novel deadlock detection algorithm and its hardware implementation are presented in this paper. The hardware deadlock detection algorithm has a run time complexity of O/sub hw/(min(m,n)), where m and n are the number of processors and resources, respectively. Previous algorithms based on a resource allocation graph have O/sub sw/(m/spl times/n) run time complexity for the worst case. We simulate a realistic example in which the hardware deadlock detection unit is applied, and demonstrate that the hardware implementation of the novel deadlock detection algorithm reduces deadlock detection time by 99.5%. Furthermore, in a realistic example, total execution time is reduced by 68.9%.