The twin-transistor noise-tolerant dynamic circuit technique

Abstract

This paper describes a new circuit technique for designing noise-tolerant dynamic logic. It is shown that voltage scaling aggravates the crosstalk noise problem and reduces circuit noise immunity, motivating the need for noise-tolerant circuit design. In a 0.35-/spl mu/m CMOS technology and at a given supply voltage, the proposed technique provides an improvement in noise immunity of 1.8/spl times/(for an AND gate) and 2.5/spl times/(for an adder carry chain) over domino at the same speed. A multiply-accumulate circuit has been designed and fabricated using a 0.35-/spl mu/m process to verify this technique. Experimental results indicate that the proposed technique provides a significant improvement in the noise immunity of dynamic circuits (>2.4x) with only a modest increase in power dissipation (15%) and no loss in throughput.