A 1.2V 250mW 14b 100MS/s digitally calibrated pipeline ADC in 90nm CMOS

Abstract

A 14b pipeline ADC is realized in 90nm CMOS at a 1.2V supply. Enabling techniques are range-scaling in the first pipeline stage with charge-reset and digital background calibration of non-linearity. The ADC achieves 73dB SNR and 91dB SFDR at 100MS/s sampling rate and 250mW power consumption. The 73dB SNDR performance is maintained within 3dB up to a Nyquist input frequency and the FOM is 0.7pJ/conv.