Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices

Abstract

The trade-offs between the technology parameters of various interconnect technologies are investigated on the basis of their impacts on the circuit performances of emerging post-CMOS devices. In this paper, carbon nanotube field-effect transistor (CNFET), nanowire-based gate-all-around (GAA) tunneling field-effect transistor (TFET), FinFET and sub-threshold CMOS circuits are studied. Each of these devices are paired with the conventional Cu/low-k interconnect, single-wall carbon nanotube (SWNT) interconnect manufactured in horizontal bundles or in a single layer, and multi-layer graphene nanoribbon (GNR) interconnect. The relative performances of all these interconnect technologies with each type of device are evaluated. The interconnect technology option that gives the best performance in terms of circuit delay, energy-per-bit and energy-delay product (EDP) is reported for each of the device technologies.