A new RTL debugging methodology in FPGA-based verification platform

TLDR

Commercial debugging tools typically limit observability to only a few hundred internal nodes in co‑simulation. The paper presents a new RTL debugging methodology for FPGA‑based verification platforms. The methodology enables internal node probing in the co‑simulation environment and lets designers control probing depth within the design hierarchy. The approach guarantees full observability with an automatically generated 32‑bit scan module, achieving 100 % design observability while keeping area and timing overheads minimal, and designers report greater comfort using RTL‑named signals compared to gate‑level names.

Abstract

In this paper we present a new RTL debugging methodology in FPGA-based verification platform. This method provides internal node probing in the co-simulation environment. Full observability is guaranteed using 32-bit scan module generated automatically. Most commercial debugging tools are limited to hundreds of internal nodes for the observability in the co-simulation. The proposed method increases the observability of design to 100%. Debugging feature named in RTL gives the benefits that designers feel more comfortable in RTL than in gate level since the signal names in gate level are complicated and incomprehensive. Designers can control the depth of probing in the design hierarchy. The overheads of area and time due to improving the design observability are turned to be small for a reasonable number of internal node probing.