Design of a 4 $\times$ 10 Gb/s VCSEL Driver Using Asymmetric Emphasis Technique in 90-nm CMOS for Optical Interconnection

Abstract

This paper describes the design and experimental results of a 4 × 10 Gb/s vertical-cavity surface-emitting laser (VCSEL) driver using the asymmetric emphasis technique. Conventional symmetric emphasis techniques can compensate for the influences of parasitic capacitances; however, they cannot compensate for the nonlinear effects of a VCSEL. To overcome this problem, an asymmetric emphasis technique that can separately control the emphasis pulses at the rising and falling edges is proposed. This allows fast transition in VCSEL output waveform suppressing ringing. A driver circuit that has two separate emphasis circuits for the rising and falling edges is proposed in order to implement the asymmetric emphasis technique. This configuration enables us to separately control the height, width, and setup time of the emphasis pulses at the rising and falling edges. The test chip fabricated by using 90-nm CMOS technology generates a clearly open optical eye at a data rate of 10 Gb/s, and we can confirm the existence of a wide phase margin by a transmission experiment.