CHOP

Abstract

This paper presents a novel constraint-driven system-level partitioning approach for behavioral specifications. The software assists a designer in partitioning behavioral specifications onto multiple chips while satisfying hard constraints which include individual chip areas, pin counts, system performance (initiation rate) and system delay. The partitioning method implemented in CHOP is based on predicting the feasibility of tentative partitions by searching through potential implementations of partitions to find combhtations which are feasible while takhtg system integration overhead into account.