A Low-Power GSM/EDGE/WCDMA Polar Transmitter in 65-nm CMOS

Abstract

A low-power, multimode polar transmitter based on a two-point injection PLL with a linearized VCO is implemented in 65-nm CMOS technology. A wideband feedback loop, nested inside the PLL with negligible area and power consumption overhead, linearizes and accurately controls the tuning characteristic of the VCO, which is a key requirement when directly modulating the oscillator. Differential delay between AM-PM paths is predictable and is self-calibrated. In WCDMA mode, the transmitter achieves 42/-58-dBc ACLR at 5/10-MHz offsets, -159-dBc/Hz receive band noise, and 2.9% EVM at 0-dBm output power while drawing 40-mA from a 3.6-V battery. The DG09 battery current is 25-mA based on a typical PA gain profile and the chip active area is 0.7-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .