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Leading-one prediction scheme for latency improvement in single datapath floating-point adders
19
Citations
8
References
2002
Year
Unknown Venue
Real Data TypeEngineeringHardware AccelerationLeading-one Prediction SchemeLatency ImprovementHigh-performance ArchitectureVlsi ArchitectureComputer EngineeringComputer ArchitectureLow LatencyComputer ScienceParallel ComputingUltra-low LatencySignal ProcessingShift AmountLeading-one PredictorActual Shift
This paper describes the design of a Leading-one Predictor (LOP) for floating-point addition, with an exact determination of the shift amount required. Previous LOP proposals produce a shift amount which might be in error by one position, so that this error has to be corrected after the addition terminates, increasing the critical path. Our design incorporates a concurrent detection of this error so that the amount of shift is corrected before the actual shift, without increasing the latency. The scheme presented here is applicable to the common case of a single datapath floating-point addition in which the output of the adder is always positive. We estimate the reduction in the critical path and the increase in area.
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