Digitally controlled 10 MHz monolithic buck converter

Abstract

This paper describes design and implementation of a 10 MHz digitally controlled buck converter realized in a standard 0.35um CMOS process. Based on a discrete-time power-stage model, we show that a 3rd-order compensator can be designed for improved transient responses and disturbance rejection compared to standard 2nd-order PID compensators. Efficient hardware realization includes a look-up table type compensator, a 10-bit hybrid DPWM (2-bit counter, 5-bit delay-line, and 3-bit dither) and a power stage optimized for efficiency