A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer

TLDR

The authors present a 60‑GHz receiver front‑end chip fabricated in a 90‑nm CMOS process. The chip integrates a low‑noise amplifier, a downconversion mixer, and a phase‑locked loop synthesizer, all implemented in a fully differential architecture to minimize parasitic effects and operate with low local‑oscillator amplitude. Measurements show a 22‑dB power gain and 8.4‑dB noise figure at 61.5 GHz, demonstrating that the chip can receive signals via an on‑chip dipole antenna and confirming the feasibility of a CMOS single‑chip 60‑GHz transceiver.

Abstract

A 60-GHz receiver (RX) front-end chip fabricated in 90 nm CMOS process is presented. The RX chip consists of an LNA, a downconversion mixer, and a phase-locked loop synthesizer. The RX chip is capable of generating LO signal from phase-locked synthesizer. The components of the RX chip employ fully differential architecture to avoid influences of parasitic components and operate with low LO signal amplitude. Measured power gain and NF of 22 dB and 8.4 dB were obtained at 61.5 GHz, respectively, and the RX chip receives a radio signal with an on-chip dipole antenna. These results indicate the possibility of realization of a CMOS single-chip 60-GHz transceiver.