Architecture of a message-driven processor

Abstract

We propole a machine architecture for a high-performaxe proceuieg node for a mueage-pas&g, MIMD concurrent computer. The principal mee,haaismn for attaining this goal are the direct execution and bufferius of meesylee and a memory-based architecture that permit@ very fast contut witches. Our architecture &o ineluder a aevel msmory orga-nis&x~ that permita both indexed and aeeecikve acceuu and that incorporates sa itwtruction buffer and me-age queer. Simulation re mite suggest that thL architecture reduccl mauge reception overheed by more thau an order of magnitude.