Experimental prototyping of beyond-CMOS nanowire computing fabrics

Abstract

Nanoscale 3D-integrated Application Specific ICs (N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ASICs) [1], a computing fabric based on semiconductor nanowire grids, is targeted as a scalable alternative to end-of-the-line CMOS. In contrast to device-centric approaches like CMOS, N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ASIC design choices across device, circuit and architecture levels are geared towards reducing manufacturing requirements while focusing on overall benefits. In this fabric, regular arrays with limited customization imply mitigated overlay precision requirements, novel circuit styles with single-type cross-nanowire FETs eliminate the need for arbitrary fine-grain sizing, doping and routing. In addition, junctionless transistors eliminate the need for stringent control of doping profiles. In this paper, we present theoretical and experimental progress towards realizing a functional N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ASIC prototype with junctionless transistors as active cross-point devices. We first validate this device concept through detailed 3D device simulations. We then present a manufacturing pathway as well as show experimental results demonstrating a proof-of-concept metal-gated junctionless nanowire device and N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ASIC tile structure with sub-30nm nanowires.