Performance estimation of complex MOS gates

Abstract

In this paper, a new efficient two-step reduction technique is proposed to estimate the performance of complex gates. A complex gate is first mapped to an equivalent NAND gate form and then the NAND gate is mapped to an inverter macromodel. Accurate reduction techniques for series-connected transistors precisely model effective transconductance, the channel length modulation effect, input terminal position dependence, parasitic capacitances, and the body effect. Adequate solutions to address these sources of delay errors, which may total 100% or more, have not been previously provided. These reduction techniques are not tied to a single macromodel, but generally are applicable to existing linear and nonlinear macromodels. Experiments with a wide range of input transitions and output loadings for various gates show nearly identical results between SPICE2 and the proposed techniques. The proposed macromodeling techniques are up to several hundred times faster than SPICE2 and up to several times faster than existing nonlinear macromodels for individual gates.