IEEE Journal of Solid-State Circuits · 1993 · 28 citations · 14 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesClock ManagementCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDigital Signal ProcessingMixed-signal Integrated Circuit DesignMixed-signal IntegrationBit Error RateCmos Logic CircuitsHigh-gain AmplifiersMonolithic ArchitectureOptical ReceiversPower Consumption
A parallel architecture for high-data-rate AGC/decision/clock-recovery circuit, recovering digital NRZ data in optical-fiber receivers, is described. Improvement over traditional architecture in throughput is achieved through the use of parallel signal paths. An experimental prototype, fabricated in a 1.2- mu m double-poly double-metal n-well CMOS process, achieves a maximum bit rate of 480 Mb/s. The chip contains variable gain amplifiers, clock recovery, and demultiplexing circuits. It yields a BER of 10/sup -11/ with an 18 mV/sub p-p/ differential input signal. The power consumption is 900 mW from a single 5 V supply.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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A 52MHz And 155MHz Clock-recovery PLL
L. DeVito, J. W. Newton, R. Croughwell et al. · 1991 · 60 citations