IEEE Journal of Solid-State Circuits · 2014 · 23 citations · 23 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureEmbedded SystemsSystem-on-chip DesignDevice ScalingDynamic Power ReductionEnergy-efficient Embedded SystemsMicroarchitecture DesignPower ManagementVoltage ScalingAdaptive Voltage ScalingArea Overhead AnalysisDynamic Frequency ScalingDynamic Voltage And Frequency ScalingGlobal Energy MinimizationPower Management TechniquesPower-performance-area TradeoffsVoltage Scaling For Process Variation
In order to optimize global energy efficiency in the context of dynamic process, voltage and temperature variations in advanced nodes, a fine-grain adaptive voltage and frequency scaling architecture is proposed for multiprocessor systems-on-chip (MPSoC), where each processing element is an independent voltage-frequency island. This architecture has been implemented on a 32 nm globally asynchronous locally-synchronous MPSoC. It shows up to 18.2% energy gains thanks to local adaptability compared with a global dynamic voltage and frequency scaling approach using 25% timing margins between slow and nominal process, by reducing margins to 60 ps of the real process. These gains are obtained for a total area overhead of 10% including local frequency/voltage actuators, sensors, and digital controller.
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