Characterizing process variation in nanometer CMOS

TLDR

Accurate process variation models are essential for correlating statistical analysis tools to hardware, requiring representation of actual silicon behavior. The paper provides an overview of test structures for characterizing statistical variation of process parameters. The authors discuss test structure design and a characterization strategy to calibrate random and layout‑dependent systematic process variation components. Measurement results from several fabricated structures in 65‑nm CMOS technologies are presented.

Abstract

The correlation of a statistical analysis tool to hardware depends on the accuracy of underlying variation models. The models should represent actual process behavior as measured in silicon. In this paper, we present an overview of test structures for characterizing statistical variation of process parameters. We discuss the test structure design and characterization strategy for calibrating random and layout dependent systematic components of process variation. We also show measurement results from several fabricated structures in 65-nm CMOS technologies.