Linearization of Efficiency-Optimized Dynamic Load Modulation Transmitter Architectures

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In this paper, a detailed linearization procedure for dynamic load modulation (DLM) transmitter architectures is proposed for the first time. Compared with the conventional single-input/single-output digital predistortion (DPD) approach used with traditional power amplifiers (PAs), the proposed linearization scheme is based on a regular memory DPD in combination with an efficiency-optimized static one-to-two mapping inverse model, which constructs the predistorted input signals to the DLM transmitter. The time-alignment issue, which is very important to this dual-input architecture, is also considered. The proposed technique is demonstrated by a 1-GHz 10-W LDMOS PA that employs a varactor-based tunable matching network. A normalized mean square error of <formula formulatype="inline"> <tex Notation="TeX">$-{\hbox {35 dB}}$</tex></formula>, and adjacent channel leakage ratio of <formula formulatype="inline"><tex Notation="TeX">$-\hbox{43 dBc}$</tex></formula> is achieved, with an average power-added efficiency of 53% for a single-carrier WCDMA signal with 7-dB peak-to-average ratio. Finally, it is shown that the time-alignment sensitivity is relaxed when the proposed linearization scheme is used. This means that the overall complexity of the transmitter implementation can be reduced. </para>