Publication | Closed Access
Tunable SEU-Tolerant Latch
11
Citations
28
References
2010
Year
Hardware SecuritySeu PulsesElectrical EngineeringSingle Event UpsetEngineeringVlsi DesignTunable Seu-tolerant LatchComputer EngineeringComputer ArchitectureSystems EngineeringSemiconductor MemoryMicroelectronicsBeyond CmosGlobal Controller
This paper presents a single event upset (SEU) hardened latch that can mitigate SEU pulses having a width less than T, where T is the longest anticipated duration of SEUs. The propose latch includes a controllable inertial delay inverter. In order to mitigate SEUs with pulse widths less than T, a global controller uses delay locked loops to control the rise and fall times of the controllable inertial delay inverter in each latch to be equal to T. This allows T to be adjustable for different applications and environmental conditions. This technique introduces little area penalty and does not adversely affect propagation delay.
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