Activity Estimation for Field-Programmable Gate Arrays

TLDR

This paper examines activity estimation techniques to identify the most suitable methods for FPGA power modeling and power‑aware CAD tool optimization. The authors compare existing activity estimation methods, then combine the best ones with two novel enhancements to develop ACE‑2.0, a publicly available tool that is benchmarked against prior tools. ACE‑2.0 achieves power estimates and savings within 1 % of simulated activities, demonstrating its accuracy and effectiveness.

Abstract

This paper examines various activity estimation techniques in order to determine which are most appropriate for use in the context of field-programmable gate arrays (FPGAs). Specifically, the paper compares how different activity estimation techniques affect the accuracy of FPGA power models and the ability of power-aware FPGA CAD tools to minimize power. After comparing various existing techniques, the most suitable existing techniques are combined with two novel enhancements to create a new activity estimation tool called ACE-2.0. Finally, the new publicly available tool is compared to existing tools to validate the improvements. Using activities estimated by ACE-2.0, the power estimates and power savings were both within 1% of the results obtained using simulated activities