A Smart Load-Pull Method to Safely Reach Optimal Matching Impedances of Power Transistors

Abstract

This paper presents a new method to find optimal load impedances of power transistors with a VNA based Load-Pull measurement setup. Most of load pull setups find the optimal load impedance of a device under test (DUT) for a given available input power. If the optimal impedance must satisfy a trade off between several parameters, such as gain compression or power added efficiency, the measurement procedure may become very time consuming. Our method automatically generates a behavioral model of the DUT. Crossing-informations from this model and measurements lead us to the good impedance optimum with a limited number of iterations.