Integrated Packaging of a 1 kW Switching Module Using a Novel Planar Integration Technology

Abstract

A metal-oxide-semiconductor field-effect transistor (MOSFET) (rating at 500 V/24 A) half-bridge power switching subassembly with gate drivers has been fabricated, employing a planar integration technology, in which an integrated power chips stage is built by embedding chips in a coplanar ceramic substrate with a metallization thin-film interconnection built up onto it. This deposited metallization not only bonds the power chips, but also provides the second-level interconnect wiring. The associated components are mounted on top of the integrated power stage. This packaging scheme results in a three-dimensional (3-D) multiple chips/components assembly with the capability of functional integration. In this paper, the electrical and thermal parameters of this packaged module have been experimentally and theoretically characterized. The procedures adopted for the defined fabrication processes are presented. In addition to the characteristics of the planar integration process, the improved electrical and thermal performance has been demonstrated.