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Enhanced damage in linear bipolar integrated circuits at low dose rate
132
Citations
13
References
1995
Year
Device ModelingElectrical EngineeringLinear BipolarEngineeringVlsi DesignDamage MechanismNanoelectronicsBias Temperature InstabilityApplied PhysicsEnhanced DamageLow Dose RatesCircuit ReliabilityIntegrated CircuitsLow Dose RateMicroelectronicsBeyond CmosSemiconductor Device
Enhanced damage at low dose rates was investigated for several different types of linear integrated circuits that were fabricated with conventional junction isolation. Although both npn and pnp transistors exhibit increased damage at low dose rate, the effect is far greater for substrate and lateral pnp transistors from these technologies. The saturation level of damage at high doses was also found to be far greater under low dose rate conditions than at high dose rates. A model for this behavior was developed that is consistent with earlier studies of MOS field oxides under low-field conditions, and accounts for the increased enhanced damage in pnp transistors.
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