Miniaturized Wilkinson power dividers utilizing capacitive loading

TLDR

The study presents a capacitive‑loaded planar Wilkinson power divider that miniaturizes the device and introduces design equations and parasitic‑reactance analysis for isolation. The divider uses coplanar waveguide input/output and asymmetric coplanar stripline transmission lines, fabricated on high‑resistivity silicon and alumina wafers for 10 GHz operation, and includes design equations and parasitic‑reactance analysis. The capacitive‑loaded divider reduces line lengths to λ/5–λ/12, achieving 74 % size reduction, return loss better than +30 dB, and insertion loss below 0.55 dB.

Abstract

The authors report the miniaturization of a planar Wilkinson power divider by capacitive loading of the quarter wave transmission lines employed in conventional Wilkinson power dividers. Reduction of the transmission line segments from /spl lambda//4 to between /spl lambda//5 and /spl lambda//12 are reported here. The input and output lines at the three ports and the lines comprising the divider itself are coplanar waveguide (CPW) and asymmetric coplanar stripline (ACPS), respectively. The 10 GHz power dividers are fabricated on high resistivity silicon (HRS) and alumina wafers. These miniaturized dividers are 74% smaller than conventional Wilkinson power dividers, and have a return loss better than +30 dB and an insertion loss less than 0.55 dB. Design equations and a discussion about the effect of parasitic reactance on the isolation are presented for the first time.