Parametric yield formulation of MOS IC's affected by mismatch effect

Abstract

A rigorous formulation of the parametric yield for very large scale integration (VLSI) designs including the mismatch effect is proposed. The theory has been carried out starting from a general statistical model relating random variations of device parameters to the stochastic behavior of process parameters. The model predicts a dependence of correlation, between devices fabricated in the same die, on their dimensions and mutual distances so that mismatch between equally designed devices can be considered as a particular case of such a model. As an application example, a new model for the autocorrelation function is proposed from which the covariance matrix of the parameters is derived. By assuming a linear approximation, a suitable formulation of the parametric yield for VLSI circuit design is obtained in terms of the covariance matrix of parameters.