Design optimization of MPEG-2 AAC decoder

Abstract

A new design for the 2-channel main-profile MPEG-2 AAC decoder is presented. To support an architectural modularity of the design, the AAC decoding algorithm has been implemented using three hardware modules: Huffman decoder, predictor, and a 20-bit programmable DSP core. The Huffman decoder module was designed to complete its job within a single clock cycle time. Also, the predictor module is executed in parallel with other modules, so that the system resource is maximally utilized. The Huffman decoder and predictor modules have been coded using VHDL, and other MPEG-2 AAC decoding routines were programmed using assembly of the DSP core. Functional simulations verified that the designed system was able to decode standard MPEG-2 AAC main-profile bitstreams using only 16.9 MIPS while it was able to maintain a high accuracy of the output PCM.