Modeling and extraction of interconnect capacitances for multilayer VLSI circuits

TLDR

The paper presents an accurate, practical method for estimating interconnect capacitances in circuit layouts. The method reduces layout geometry into base elements with vertical profiles, applies analytical 2D models from the TDTL simulator transformed into 3D, and stores coefficients in the CUP tool linked to HILEX to compute node‑level capacitances for netlist generation. The extracted capacitances agree with measured data and 3D simulations within 10%, enabling accurate node‑level capacitance extraction for circuit netlists.

Abstract

We report an accurate and practical method of estimating interconnect capacitances for a given circuit layout. The method allows extraction of the complete circuit level capacitances at each node in the circuit. The layout geometry is reduced into base elements that consist of different vertical profiles at each node in the layout. Accurate analytical models are developed for calculating capacitances of multilayer structures using a 2D capacitance simulator TDTL. These models are then transformed into 3D geometry. The resulting model capacitance values are found to be within 10% of both the measured data and 3D simulations of structures that are prevalent in typical VLSI chips. The models and their coefficients for different vertical profiles are stored in the capacitance extraction tool CUP, which is coupled to the layout extractor HILEX. As each base element has a unique vertical profile, the corresponding capacitance can easily be calculated for each node that is then written out to a circuit netlist. The comparisons of the models with the measured data, as well as 3D simulations results, are also discussed.