An accurate statistical yield model for CMOS current-steering D/A converters

Abstract

To obtain a high resolution CMOS current-steering digital-to-analog converter, the matching behavior of the current source transistors is one of the key issues in the design. At this moment, these matching properties are taken into account by the use of time consuming and CPU intensive Monte Carlo simulations. In this paper a formula is derived that allows us to accurately describe the impact of the mismatch on the INL (integral non-linearity) yield of current-steering D/A converters without any loss of design time.