VLSI implementation of online digital watermarking technique with difference encoding for 8-bit gray scale images

Abstract

Digital watermarking is a technique of embedding imperceptible information into digital documents. In this paper, a VLSI implementation of the digital watermarking technique is presented for 8 bit gray scale images. This implementation of fragile invisible watermarking is carried out in the spatial domain. The standard ASIC design flow for a 0.13 /spl mu/m CMOS technology has been used to implement the algorithm. The area of the chip is 3453/spl times/3453 /spl mu/m/sup 2/ and the power consumption is 37.6 /spl mu/W.