Design, Simulation and Testing of a High Speed Low Power 15-4 Compressor for High Speed Multiplication Applications

Abstract

The paper presents a novel high speed and low power 15-4 Compressor for high speed and low power multiplication applications. The proposed compressor uses bit sliced adder architecture to exploit the parallelism in the computation of sum of 15 input bits by five full adders. The newly proposed compressor is also centered around the design of a novel 5-3 compressor that attempts to minimize the stage delays of a conventional 5-3 compressor that is designed using single bit full adder and half adder architectures. The proposed 15-4 compressor uses the minimum number of hardware resources so far as the logic level architecture of the design is concerned. The proposed compressor is tested using 14 transistor and 10 transistor adder designs reported in literature. The power delay product of the proposed compressor is found to be equal to as low as 0.98fJ using 10T adder design and 0.46fJ using 14T adder design. The whole simulation has been carried out using TSPICE using 0.35 mum technology.